The computer and electronics industry demand of increasing its whole speed performance as well as it's cost down for fabricating integrated circuits. As far as a computer technology is concerned, there is no doubt that the DRAM integrated circuit plays a crucial role because DRAMs used in the computer are very large, and thus DRAMs play a vital factor which determines the computer's performance. Hence, pursuing the miniaturization of the DRAM device so as to reduce the cost as well as high-speed performance are almost the ultimate goals.
Considering miniaturization of the device or the high-speed performance, the DRAM cell's storage capacity is a major factor which needs to be considered. The capacitor is formed with a storage node, a cell plate, and an intervening dielectric layer. Thus the storage capacity could be increased by making the capacitor dielectric thinner, by using an insulator with a larger dielectric constant, or by increasing the area of the capacitor. The first two options are not viable, since capacitor dielectrics thinner than those now being used in DRAM cells will suffer leakage due to Fowler-Nordheim tunneling. The suffering from a higher leakage for using a larger dielectric constant insulator is also reported in some research. Thus, for one-transistor DRAM, a large surface area of the storage node and cell plate are necessary in order to provide high capacitance and therefore optimal performance of the capacitor. However, a large surface area of the storage node and cell plate are conflicted with the shrinkage of the feature size of the DRAM.
Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the semiconductor substrate on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the semiconductor substrate. When so doing, the storage node and the cell plate are typically wrapped around the other, forming what is known as a stacked capacitor.
However, by using a conventional method, the aspect ratio of the contact hole for forming such a stacked capacitor, tends to gradually increase in accordance with the use of three dimensional capacitor structures in the vertical direction. The decrease of the contact-hole diameter and its high aspect ratio impose a large burden on subsequent photolithography and etching steps. If the photolithography is carried out without accurate alignment, the contact hole cannot be formed at a desired site. Also, in the case of a high aspect ratio, it is likely that the etching process of the contact hole will cease before the interlayer insulation film is entirely removed.
Recently, a concept of `landing pad` is prone to improve the DRAM capacitor manufacturing process so as to resolve the misalignment issue. The U.S. Pat. No. 5,780,339, entitled "Method for fabricating a semiconductor memory cell in a DRAM." is an example. See FIG. 1.
However, to fabricate a DRAM capacitor in prior art patent, two mask layers are still required for forming the storage node contact and storage node. In addition, the patent didn't fully utilize the two dielectric layers 22 and 28, and thus the issue of the topology height is still exist for making large capacitor area.
Consequently, an improved method is needed to overcome the above-discussed problems.